1. Field of the Invention
The present invention relates to a frequency doubler, a signal generator, an optical transmitter, and an optical communication apparatus.
2. Description of the Related Art
The development of an ultrafast optical communication system has been in progress, leading to practical application of a system achieving a transmission rate of 40 Gb/s. Meanwhile, a quest for high-speed processing by an electronic circuit has completed the first stage of progress, and has been replaced with an effort to increase the processing speed of a system through a well devised circuit. A typical example of such a well devised circuit is a serializer/deserializer, which is a central component of a transmitter/receiver.
A complementary metal oxide semiconductor (CMOS) demonstrating superior power consumption performance has difficulty achieving a desirable transmission rate, which has lead to attempts to achieve faster operation by combining the CMOS with a multiplexer (MUX) that employs a compound semiconductor. In addition, the adoption of a half-rate configuration in a serializer is an important technique for achieving faster operation.
To generate a high-speed clock used in a serializer and such, a frequency doubler (clock doubler) is used as a circuit that multiplies the original oscillation (see, e.g., Japanese Patent Application Laid-Open Publication Nos. 2003-198339 and 2000-183700). The frequency doubler has a configuration, for example, such that one branch of a clock signal is delayed through a delay circuit by T/4 (hereinafter, T denotes the period of a clock signal) and the exclusive-OR of the clock signal is calculated.
According to the conventional technique above, however, when the delay rate of each clock signal input to a calculating circuit calculating the exclusive-OR shifts from T/4 (which is 2.5 ps if a transmission rate is 100 Gb/s), the duty cycle of a clock signal output from the calculating circuit consequently shifts, which is a problem. For example, depending on the presence/absence of an error correction process (forward error correction (FEC)), multirate transmission may be desirable in an optical communication system.
In multirate transmission, T/4 is not a fixed value and hence, a fixed delay rate at a delay circuit that delays one of the branched clock signals is not compatible with multirate transmission. Further, a fixed delay rate at the delay circuit cannot cope with a change in the delay rate clock signals resulting from fabrication variations and time-dependent changes in a circuit.
A shift in the delay rate of each clock signal input to the calculating circuit calculating the exclusive-OR from an optimum point (e.g., T/4) results in a shift in the duty cycle of a clock signal output from the calculating circuit. Consequently, in a serializer, etc., that employs a frequency doubler, a problem arises in that a shift in the duty of the serial signal output occurs and the quality of the signal degrades.